This course aims to teach learners about the dramatic improvements in System-on-Chip (SoC) validation and debug through the use of Quick Error Detection (QED) and Symbolic QED. The learning outcomes include understanding the challenges of post-silicon validation, improving error detection latency, and enhancing bug localization. The course covers skills such as using QED programs for validation, implementing diversity-enhanced QED, and applying Symbolic Quick Error Detection. The teaching method involves presenting real-world examples, comparing traditional methods with QED approaches, and discussing the benefits of QED in detecting logic and power management bugs. This course is intended for professionals working in the field of semiconductor design, validation engineers, hardware engineers, and anyone interested in improving SoC validation processes.
Stanford Seminar - QED and Symbolic QED- Dramatic Improvements in SoC Validation and Debug
Stanford University via YouTube
Overview
Syllabus
Introduction.
Staggering IC Complexity.
Post-Silicon Validation Critical.
Post-Silicon Validation Difficult.
Scalability Barriers.
Bigger Obstacles at System Level.
Bug Example.
QED Example: Duplicate & Check Validation program.
QED Example: Duplicate & Check QED Trace.
QED Improves Coverage.
Diversity-Enhanced QED.
QED: Proactive Load & Check.
QED Coverage Considerations.
Error Detection Latency vs. Intrusiveness Improved error detection latency.
Intel® Core™ i7 Hardware.
8-Core QED: Difficult Logic Bugs.
8-Core QED: Power Management Bugs 100%.
Hybrid QED: Logic Bug Results.
Bug Localization.
Symbolic Quick Error Detection.
Traditional Bounded Model Checking.
BOUNDED MODEL CHECKING (BMC).
Traditional BMC vs. Symbolic QED.
BMC Challenge (1): Property.
Universal Property: QED Check.
QED Module.
QED Guarantees Quick Detection.
Partial Instantiation.
Taught by
Stanford Online
